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Ordering number : EN3355B
CMOS IC
LC7216M
PLL Frequency Synthesizer for Electronic Tuning in AV Systems
Overview
The LC7216M is PLL frequency synthesizers for electronic tuning. The LC7216M is optimal for AM/FM tuner circuits that require high mounting densities.
Package Dimensions
unit: mm 3036B-MFP20
[LC7216M]
20 11
Features
* This product feature a rich set of built-in functions for AV applications, including reference frequency and unlock detection circuits, I/O ports and a generalpurpose counter.
6.35 0.15 0.625
Functions
* Programmable dividers -- FMIN pin: 130 MHz at 70 mVrms and 160 MHz at 110 mVrms input (built-in prescaler) -- AMIN pin: Pulse swallower and direct division techniques * Reference frequencies: Ten selectable frequencies: 1, 5, 9, 10, 3.125, 6.25, 12.5 25, 50 and 100 kHz * Output ports: 5 pins Complementary outputs: 2 pins N-channel open drain outputs: 3 pins * Input ports: 2 pins * General-purpose counter: For measuring IF and other signals (Also used for station detection when functioning as an IF counter.) -- HCTR pin: Frequency measurement (for inputs up to 70 MHz) -- LCTR pin: Frequency and period measurement * PLL unlock detection circuit Detects phase differences of 0.55, 1.11, 2.22 and 3.33 s. * Package: MFP20
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
1
12.6 1.5
10
1.8 max
0.35
1.27
0.59
0.1
5.4
SANYO: MFP20
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
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31299RM(OT)/02793JN KAWA/4280TA, TS KAWA No. 3355-1/15
7.6
LC7216M Block Diagram
Pin Symbols XIN, XOUT: FMIN, AMIN: CE, CL, DI, DO: OUT1 to OUT5: IN0, IN1: HCTR, LCTR: PD: Crystal oscillator (7.2 MHz) Local oscillator signal input Serial data I/O Output ports Input ports General-purpose counter inputs Charge pump output
Note: Crystal oscillator example: 7.200 MHz, CL16 pF (C = 27 pF) *LN-X-0702 (NR-18 type) *LN-P-0001 (AT-51 type)
Manufactured by: NIHON DEMPA KOGYO CO., LTD.
Pin Assignment
No. 3355-2/15
LC7216M
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 VOUT1 Output voltage VOUT2 VOUT3 VOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD CE, CL, DI, IN0, IN1 Input pins other than VIN1 DO OUT1, OUT2 OUT3 to OUT5 Output pins other than VOUT1, VOUT2 and VOUT3 Ta 85C Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 200 -40 to +85 -55 to +125 Unit V V V V V V V mW C C
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V
Parameter Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 VOUT1 VOUT2 fIN1 fIN2 Input frequency fIN3 fIN4 fIN5 fIN6 Crystal oscillators for which operation is guaranteed Xtal VIN1 VIN2 Input amplitude VIN3 VIN4 VIN5 Note: 1. DV 1 0 0 SP * 1 0 Input frequency 10 to 130 (160) MHz 2 to 40 MHz 0.5 to 10 MHz 1/2 divider 1/16, 17 swallow 12-bit main divider Input pin FMIN AMIN AMIN VDD VDD: Crystal oscillator guaranteed operation CE, CL, DI, IN0, IN1 LCTR: Pulse waveform, DC coupling*4 CE, CL, DI, IN0, IN1 LCTR*4 DO OUT3 to OUT5 XIN: Sine wave capacitor coupling, VDD2 FMIN: Sine wave capacitor coupling, VDD1*1 AMIN: Sine wave capacitor coupling, VDD1*1 HCTR: Sine wave capacitor coupling, VDD1*2 LCTR: Sine wave capacitor coupling, VDD1*3 LCTR: Pulse wave DC coupling, VDD1*4 XIN-XOUT: CI 50 XIN: Sine wave capacitor coupling, VDD1 FMIN: Sine wave capacitor coupling, VDD1 AMIN: Sine wave capacitor coupling, VDD1 HCTR: Sine wave capacitor coupling, VDD1*2 LCTR: Sine wave capacitor coupling, VDD1*3 1.0 10 0.5 10 15 1.0 3.0 0.5 0.07 (0.11)*5 0.07 0.07 (0.11)*6 0.07 7.2 7.2 Conditions Ratings min 4.5 3.5 2.2 0.7 VDD1 0 0 typ max 6.5 6.5 6.5 VDD1 0.7 0.3 VDD1 6.5 13 8.0 130 (160)*5 40 60 (70)*6 500 20 x 103 8.0 1.5 0.5 0.5 0.5 0.5 Unit V V V V V V V V MHz MHz MHz MHz kHz Hz MHz Vrms Vrms Vrms Vrms Vrms
Supply voltage
Input high level voltage
Input low level voltage
Output voltage
q
-- --
q q
--
q q q
2. 3. 4. 5. 6.
DV and SP are bits in the serial data. *: don't care Frequency measurement Frequency measurement Period measurement fIN2: 10 to 160 MHz/VIN2 0.11 Vrms (minimum) fIN4: 10 to 70 MHz/VIN4 0.11 Vrms (minimum)
No. 3355-3/15
LC7216M Electrical Characteristics for the Allowable Operating Ranges
Parameter Symbol Rf1 Rf2 Internal feedback resistance Rf3 Rf4 Rf5 Hysteresis VH IIH1 IIH2 Input high level current IIH3 IIH4 IIH5 IIL1 IIL2 Input low level current IIL3 IIL4 IIL5 Output high level voltage VOH1 VOH2 VOL1 Output low level voltage VOL2 VOL3 VOL4 Output off leakage current Three-state high level off leakage current Three-state low level off leakage current Input capacitance IOFF1 IOFF2 IOFFH IOFFL CIN IDD1 Current drain IDD2 XIN FMIN AMIN HCTR LCTR LCTR CE, CL, DI: VI = 6.5 V IN0, IN1: VI = VDD XIN: VI = VDD FMIN, AMIN: VI = VDD HCTR, LCTR: VI = VDD CE, CL, DI: VI = VSS IN0, IN1: VI = VSS XIN: VI = VSS FMIN, AMIN: VI = VSS HCTR, LCTR: VI = VSS OUT1, OUT2: IO = 1 mA PD: IO = 0.5 mA OUT1, OUT2: IO = 1 mA PD: IO = 0.5 mA OUT3 to OUT5: IO = 5 mA DO: IO = 5 mA OUT3 to OUT5 = 13 V DO: VO = 6.5 V PD: VO = VDD PD: VO = VSS FMIN, HCTR VDD: fIN2 = 130 MHz, VIN2 = 70 mVrms, with a 7.2 MHz crystal, other input pins at VSS, output pins open VDD: PLL block stopped (PLL inhibit state), crystal oscillator operating, with a 7.2 MHz crystal, other input pins at VSS, output pins open 1 0.01 0.01 2 20 VDD - 1.0 VDD - 1.0 1.0 1.0 1.0 1.0 5.0 5.0 10.0 10.0 3 30 0.1 VDD Conditions Ratings min typ 1.0 500 500 500 500 0.6 VDD 5.0 5.0 20 40 40 5.0 5.0 20 40 40 max Unit M k k k k V A A A A A A A A A A V V V V V V A A nA nA pF mA
1.0
mA
Note: A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS potentials.
No. 3355-4/15
LC7216M Pin Functions
Pin No. 1 20 Symbol XIN XOUT I/O Input Output Xtal OSC Type Function * Connections for a 7.2 MHz crystal oscillator
16
FMIN
Input
Local oscillator signal input
* FMIN is selected when DV in the serial input data is set to 1. * Input frequency range: 10 to 130 MHz (70 mVrms minimum) * The signal passes through an internal divide-by-two prescaler and is then supplied to the swallow counter. * Although the divisor setting is in the range 256 to 65,536, the actual divisor will be twice the set value due to the presence of the internal divide-by-two prescaler. * AMIN is selected when DV in the serial input data is set to 0. * When SP in the serial input data is set to 1: -- Input frequency range: 2 to 40 MHz (70 mVrms minimum). -- The signal is supplied directly to the swallow counter without passing through the internal divide-by-two prescaler. -- The divisor setting is in the range 256 to 65,536 and the actual divisor will be the value set. * When SP in the serial input data is set to 0: -- Input frequency range: 0.5 to 10 MHz (70 mVrms minimum). -- The signal is supplied directly to a 12-bit programmable divider. -- The divisor setting is in the range 4 to 4,096 and the actual divisor will be the value set.
15
AMIN
Input
Local oscillator signal input
18
PD
Three-state
Charge pump outputs
* PLL charge pump outputs. High levels are output from PD when the local oscillator frequency divided by n is higher than the reference frequency, and low levels are output when that frequency is lower than the reference frequency. This pin go to the floating state when the frequencies agree.
17
VDD
--
Power supply
* The LC7216M power supply pin. A voltage of between 4.5 and 6.5 V must be provided when the PLL is operating. The supply voltage can be lowered to 3.5 V when only operating the crystal oscillator circuit to acquire the controller clock and the clock time base outputs. * The LC7216M ground pin * This pin must be set high when inputting serial data (via DI) or when outputting serial data (via DO). * The clock input used for data signal synchronization during serial data input (via DI) or output (via DO).
19
VSS CE
--
Ground
2
Input*
Chip enable
4
CL
Input*
Clock
3
DI
Input*
Input data
* Input pin used when transferring serial data from the controller to the LC7216M. * A total of 36 bits of data must be supplied to set up the LC7216M initial state.
5
DO
Output (N-channel open drain)
Output data
* Output pin used when transferring serial data to the controller from the LC7216M. * A total of 28 bits from an internal shift register can be output in synchronization with the CL signal.
Note: * The high and low level input voltages for the CE, CL, DI, IN0 and IN1 pins are VIH = 2.2 to 6.5 V and VIL = 0 to 0.7 V, regardless of the power supply voltage VDD.
Continued on next page. No. 3355-5/15
LC7216M
Continued from preceding page.
Pin No. Symbol I/O Type Function
10 11 12 13 14
OUT1 OUT2 OUT3 OUT4 OUT5
Output*1
Output port
* These pins latch bits O1 to O5 in the serial data transferred from the controller, invert that data and output the inverted data in parallel. * OUT1 and OUT2 are complementary outputs. * OUT3, OUT4, and OUT5 are N-channel open drain outputs that can handle up to 13 V.
6 7
IN0 IN1
Input*2
Input port
* The values of the IN0 and IN1 input ports can be converted from parallel to serial and output from the DO output pin.
14
HCTR
Input
General-purpose counter Frequency measurement signal input pin
* HCTR is selected when SC in the serial input data is set to 1. * Input frequency range: 10 to 60 MHz (70 mVrms minimum) * The signal is supplied to a general-purpose 20-bit binary counter after passing through a divide-by-eight circuit. Therefore, the value of the counter is 1/8 of the frequency actually input to HCTR. * When HCTR is selected the LC7216M will function in frequency measurement mode and the measurement period can be selected to be either 60 or 120 ms. (GT = 0: 60 ms, 1: 120 ms) * The result of the measurement (the value of the general-purpose counter) can be output MSB first from the DO output pin.
13
LCTR
Input
General-purpose counter Frequency or period measurement signal input pin
* LCTR is selected when SC in the serial input data is set to 0. * When SF in the serial input data is set to 1: -- Frequency measurement mode is selected. -- Input frequency range: 15 to 500 kHz (70 mVrms minimum). -- The signal is supplied directly to the general-purpose counter without passing through the internal divide-by-eight circuit. -- The measurement period is the same as for HCTR. * When SF in the serial input data is set to 0: -- Period measurement mode is selected. -- Input frequency range: 1 Hz to 20 kHz (VIH = 0.7 VDD minimum, VIL = 0.3*VDD maximum) -- The measurement can be selected to be for one or two cycles. If two cycle measurement is selected the input frequency range becomes 2 Hz to 20 kHz. (GT = 0: one cycle, 1: two cycles) * Measurement results are output in the same manner as HCTR measurement results.
Note: *1. Since the output port states are undefined when power is first applied, transfer the control data quickly. *2. The high and low level input voltages for the CE, CL, DI, IN0 and IN1 pins are VIH = 2.2 to 6.5 V and VIL = 0 to 0.7 V, regardless of the power supply voltage VDD.
Control Data Format (serial input data)
Input starting with D0.
No. 3355-6/15
LC7216M The LC7216M control data consists of 36 bits. All 36 bits must be input after power is applied to set up the LC7216M initial state. This is because the last two bits, while being unrelated to user functions, are data that switches the LSI test modes. Once the LC7216M has been initialized, the contents of the first 24 bits (D0 to CTEN) can be changed without changing the contents of the last 12 bits (R0 to T1) by inputting data to DI in serial data input mode.
No. Control block/data Description * This data sets up the programmable divider. D0 to D15 is a binary value with D15 as the MSB. The position of the LSB is changed by DV and SP as listed in the table below. Programmable divider data D0 to D15 DV 1 0 0 SP * 1 0 LSB D0 D0 D4 Divisor setting 256 to 65536 256 to 65536 4 to 4096 Actual divisor Twice the set value The set value The set value DV SP Related data
(1)
* don't care When D4 is the LSB, bits D0 to D3 are ignored.
(2)
Output port data O1 to O5
* Data that determines the states of the output ports OUT1 to OUT5. O1 determines the OUT1 pin output. However, note that when O1 is 0, OUT1 will output a high level, and when O1 is 1, OUT1 will output a low level. O2 to O5 function in the same manner. * These can be used for a wide range of purposes, including, for example, band switching signals.
(3)
General-purpose counter initial data CTEN
* Data that determines the operation of the general-purpose counter. When CTEN is 0, the 20-bit binary counter (the general-purpose counter) is reset and the HCTR and LCTR pins are pulled down to ground. When CTEN is set to 1, the general-purpose counter reset state is cleared and the counter operates according to the SC bit (the general-purpose selection data). In this state, the general-purpose counter will count either the HCTR or LCTR input signal. * Since the general-purpose counter is reset by setting CTEN to 0, the result of a count operation must be sent to the controller while CTEN is still 1.
SC SF GT
* Data that selects one of the ten LC7216M reference frequencies or sets the LC7216M to backup mode in which PLL operation is disabled. R0 0 0 0 0 0 0 Reference frequency data R0 to R3 0 0 1 1 1 1 1 1 1 1 R1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PLL inhibit state* Reference frequency (kHz) 100 50 25 25 12.5 6.25 3.125 3.125 10 9 5 1
(4)
Note: * PLL inhibit (backup mode) The programmable divider block is turned off, both the FMIN and AMIN pins are pulled down to ground, and the charge pump outputs go to the floating state.
Continued on next page. No. 3355-7/15
LC7216M
Continued from preceding page.
No. Control block/data Description * DV selects the local oscillator input pin. (FMIN or AMIN) * SP switches the input frequency range when AMIN is selected. (5) Divider selection data DV Sensitivity selection data SP DV 1 0 0 SP * 1 0 Input pin FMIN AMIN AMIN Input frequency range (MHz) 10 to 130 2 to 40 0.5 to 10 Related data
(6)
* don't care * SC selects the input pin (HCTR or LCTR) for the general-purpose counter. * SF selects the measurement type (frequency or period) when LCTR is selected. When HCTR is selected, SF is ignored and the LC7218 operates in frequency measurement mode. DV 1 0 0 SP * 1 0 Input pin HCTR LCTR LCTR Measurement type Frequency measurement (sine wave) Frequency measurement (sine wave) Period measurement (pulse waveform) CTEN GT
(7)
General-purpose counter input pin selection data SC General-purpose counter frequency/period mode switching data SF
(8)
* don't care
(9)
General-purpose counter count time selection data GT
* GT selects the measurement time in frequency measurement mode and the number of periods in period measurement mode. GT = 0: 60 ms/one period GT = 1: 120 ms/two periods (frequency measurement/period measurement) * TB is set to 0 * T0 and T1 switch the LSI between test and normal operating modes. The test modes and have no user related functions. Both T0 and T1 must always be set to 0. Be sure to set both T0 and T1 to 0 after power is applied.
CTEN SC SF
(10)
TB LSI test mode control data T0, T1
(11)
DO Output Format (serial data output)
Output from I0
The LC7216M includes a 28-bit internal shift register that can be used to output the following data from DO: the IN0 and IN1 input port states, the general-purpose counter (20-bit binary counter) and the unlock detection circuit state. The contents of the shift register is latched at the point that serial data output mode is selected.
No. (1) Data Input port data I0 and I1 General-purpose counter binary data C19 to C0 Description * The values of the IN0 and IN1 input ports are latched into I0 and I1. I0 IN0, I1 IN1 * The C19 to C0 data is latched from value of the general-purpose 20-bit binary counter. C19 20-bit binary counter MSB C0 20-bit binary counter LSB * The UL3 to UL0 data is latched from the unlock detection circuit. UL0: 1.11 s UL1: 2.22 s These bits are set to 1 if a phase difference in excess of these times was detected. UL2: 3.33 s (for a 7.2 MHz crystal) UL3: 0.55 s
(2)
(3)
PLL unlock state data UL3 to UL0
No. 3355-8/15
LC7216M Serial Data I/O Methods The LC7216M supports a total of three I/O modes: two control data input (serial data input) modes and one DO output (serial data output) mode. Data I/O is performed after the mode has been determined. The mode is selected by four data items (A0 to A3) synchronized with a clock (the CL pin) applied before the CE pin is set high. The mode is determined when the CE pin goes high.
Mode A3 A2 A1 A0 Item Function * This mode is used to input all 36 bits of the control data (serial input data). This mode is used for initialization following power on and to change data that cannot be changed in mode 2. All 36 bits of the control data is input from the LC7216M DI pin. * This mode is used to input a subset (24 bits) of the control data (serial input data). This mode is used to change three data items: the programmable divider data (D0 to D15), the output port data (O1 to O5) and the general-purpose counter start data (CTEN), for a total of 24 bits. The other 12 bits of control data are not changed by a mode 2 operation. (Use mode 1 when the other 12 bits must be changed.) * The DO output mode (serial data output) is used to output three data items from the DO pin: the input port data, the general-purpose counter binary data and the PLL unlock state data. * This mode is invalid and does not support any data input or output operations.
1
0
0
0
1
Serial data input (all bits)
2
0
0
1
0
Serial data input (partial input)
3
0 0 to 0
0 1 to 0
1 0 to 0
1 0 to 0
Serial data output Invalid setting
Mode determined.
1. In the serial data input modes (modes 1 and 2), t1 1.5 s, t2 0 s, t3 1.5 s, and t4 < 1.5 s.
Internal data
* Mode 1: A total of 40 bits, the four mode selection bits and the 36 control data bits (from D0 to T1), are input from the DI pin in synchronization with the clock (CL) signal. * Mode 2: A total of 28 bits, the four mode selection bits and 24 control data bits (from D0 to CTEN), are input from the DI pin in synchronization with the clock (CL) signal.
No. 3355-9/15
LC7216M 2. In serial data output mode (mode 3), t1 1.5 s, t2 0 s, t3 1.5 s, and t5 < 1.5 s. (However, note that since the DO pin is an n-channel open drain output, the transition time depends on the value of the pull-up resistor.)
* Mode 3: Serial output mode (mode 3) is selected by the four bits of mode selection data. When the CE pin goes high, I0 is output from the DO pin. After that, the internal shift register is shifted and the next bit is output from the DO pin on each falling edge of the CL signal. (Thus 27 clock cycles are required to output all data through the UL0 bit after CE goes high.) When this mode is selected, at the point the CE pin falls to the low level, the DO pin will be forcibly set to the high level. The DO pin will go low if the IN0 pin input changes state or if a general-purpose counter measurement completes. (General-purpose counter completion takes precedence over changes in the IN0 pin signal.) Structure of the Programmable Divider
DV (A) (B) (C) 1 0 0
SP * 1 0 FMIN AMIN AMIN
Input pin
Divisor setting 256 to 65536 256 to 65536 4 to 4096
Actual divisor Twice the set value The set value The set value
Input frequency range (MHz) 10 to 130 2 to 40 0.5 to 10
Note: 1. The actual divisor will be twice the set value when FMIN (A) is used. For example, if the divisor setting is 1000 the actual divisor will be 2000 and if the divisor setting is 1001 the actual divisor will be 2002. In other words, the channel skip will be twice the reference frequency. 2. To set the channel skips of 1, 5 and 9 kHz using FMIN (A), the crystal oscillator should be changed to 3.6 MHz. However, the times listed in the table that follows change since they are referenced to the crystal oscillator frequency. Note that care must be taken to prevent overtone oscillation when a 3.6 MHz crystal oscillator is used.
No. 3355-10/15
LC7216M
Xtal 7.2 MHz 120/60 ms 900 kHz 100, 50, 25, ......... 10, 9, 5, 1 kHz t1 1.5 s, t3 1.5 s 3.6 MHz 240/120 ms 450 kHz 50, 25, 12, 5, .......... 5, 4.5, 2.5, 0.5 kHz t1 3.0 s, t3 3.0 s
Item Frequency measurement period Frequency measurement check signal Reference frequencies Serial data I/O (CL)
Structure of the General-Purpose Counter
Input signal switching gate
General-purpose counter (20-bit binary counter)
Two period/one period extraction circuit
DO pin Check signal (900 kHz)
SC S1 S2 S3 1 0 0
SF * 1 0 HCTR LCTR LCTR
Input pin
Measurement item Frequency measurement Frequency measurement Period measurement
Measurement frequency range 10 to 60 MHz (sine wave) 15 to 500 kHz (sine wave) 1 Hz to 20 kHz (pulse wave)
GT (1/0) 120 m/60 ms 120 m/60 ms Two periods/one period
The LC7216M general-purpose counter is a 20-bit binary counter. The value of the counter can be read out, msb first, from the DO pin. When the general-purpose counter is used for frequency measurement, GT selects the measurement period to be one of two periods, 60 or 120 ms. The frequency of the signal input to the HCTR or LCTR pin can be measured by determining the number of pulses input to the general-purpose counter during the measurement period. When the general-purpose counter is used for period measurement, the period of the signal input to the LCTR pin can be measured by determining the number of check signal (900 kHz) cycles input to the general-purpose counter during one or two periods of the signal input to the LCTR pin. The general-purpose counter is started by setting CTEN to 1 in the serial data. While the serial data is acquired internally in the LC7216M at the point the CE signal goes from high to low, the input to the HCTR or LCTR pin must be provided within 10 ms after CE goes low.
No. 3355-11/15
LC7216M Next, the value of the general-purpose counter after the measurement completes must be read out while CTEN is still 1. (The general-purpose counter is reset when CTEN is set to 0.) Another point that requires care here is that before starting the general-purpose counter, it must be reset by setting CTEN to 0. Note that although signals input to the LCTR pin are transmitted directly to the general-purpose counter, signals input to the HCTR pin are divided by eight internally before being transmitted to the general-purpose counter. Therefore the value of the general-purpose counter will be 1/8 of the actual frequency input to the HCTR pin. When counting intermediate frequency signals, always have the controller first check for the presence of the IF-IC SD (station detect) signal and then only turn on the IF counter buffer output if the SD signal was present. Auto-search techniques that only use an IF count are subject to stopping at frequencies where there is no station due to leakage output from the IF counter buffer.
Frequency measurement time
70 mVrms or greater (frequency measurement)
0.7VDD (min.)
(period measurement) 0.3VDD (max.)
Period measurement time 900 kHz (check signal)
Note that although the DO pin is forced to the high level when the general-purpose counter is started (when CTEN is set to 1), the DO pin automatically goes low when the measurement completes (after either 60 or 120 ms has elapsed or when a signal has been applied for one or two periods). Therefore the DO pin can be used to check for measurement completion. 1. When the general-purpose is not used (when CTEN is 0) the DO pin can be used to check for changes in external signals.
: Control data (0)
Pin outputs
Mode 1 or 2 (data input)
Mode 3 (data output)
Mode 1 or 2 (data input)
Mode 3 (data output)
Mode 1 or 2 (data input)
* When mode 3 is specified and data is output through DO, DO will automatically go high after data output has completed, i.e., when CE goes low. * After that, DO goes low automatically when the IN0 signal changes state. (That is, DO can be used to check for changes in an external signal input to IN0.)
No. 3355-12/15
LC7216M 2. When the general-purpose counter is used the DO pin can be used to check for completion of the general-purpose counter measurement.
*DO going low due to changes in IN0 is disabled. Internal counter gate (GT)
Measurement period Measurement complete Measurement period Measurement complete
: Counter data
: Internal state
Pin outputs
Measurement complete signal
Mode 1 or 2 (data input) CTEN = 1
Mode 3 Mode 1 or 2 (data output) (data input) * Output of the measurement result CTEN = 0
Mode 1 or 2 (data input) CTEN = 1
Mode 1 or 2 (data input) CTEN = 0
* When CTEN is set to 1, DO going low due to changes in IN0 is disabled and DO is set high automatically. * DO is automatically set low when the general-purpose counter measurement completes. (That is, DO can be used to check for measurement completion.) PLL Unlock Data Read Out Procedure
Mode 1 or 2 (data input) Mode 1 or 2 (data input) Mode 3 (data output)
Data output for UL(n) = 1 Each bit is set to 1 according to oERROR as described above.
The internal data UL(n) is set on the rising edge of oERROR and reset on the rising edge of CE . The oERROR data UL(n) from before the previous CE rising edge can be read out in mode 3 (data output). In the example above, the data from the period between t0 and t1 is read out.
oERROR < 0.55 s oERROR < 1.11 s oERROR < 2.22 s oERROR < 3.33 s oERROR UL (n) 3210 0000 1000 1001 1011 1111
0.55 s 1.11 s 2.22 s 3.33 s
UL0 : 1.11 s UL1 : 2.22 s UL2 : 3.33 s UL3 : 0.55 s
Each bit is set to 1 according to oERROR as described above.
oERROR: the phase difference (for a 7.2 MHz crystal)
No. 3355-13/15
LC7216M Sample Application System FM/AM (When IF count is performed)
Note: 1. The coupling capacitors used on the FMIN, AMIN, HCTR, and LCTR pins should be between 50 and 100 pF. However, a 1000 pF capacitor should be used for LCTR if frequencies under 100 kHz are to be used. 2. Coupling capacitors should be located as close to their pin as possible. 3. When counting intermediate frequency signals, always have the controller first check for the presence of the IF-IC SD signal and then only turn on the IF counter buffer output if the SD signal was present. 1. FM, 100 kHz steps When the FM RF = 90 MHz (IF = +10.7 MHz) FM VCO = 100.7 MHz PLL fref = 50 kHz DV = 1, SP = * (FMIN selected) Programmable divider divisor Set N = 1007 (decimal). 2. AM, 10 kHz steps When the AM RF = 1000 kHz (IF = +450 kHz) AM VCO = 1450 kHz PLL fref = 10 kHz DV = 0, SP = 0 (AMIN, low speed measurement selected) Programmable divider divisor Set N = 145 (decimal). *: Do not care
No. 3355-14/15
LC7216M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 1999. Specifications and information herein are subject to change without notice. PS No. 3355-15/15

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